Designers handle aging using various heuristics (“educated guesswork”), which typically add a safety margin to designs. But it’s not accurate, and leaves money on the table by increasing surface area of the chip more than necessary.
Moreover, margin typically isn’t just one thing. It’s actually a stack.“The foundry, with the models that they give us, includes a little bit of padding to cover themselves,” said ANSYS’ Geada. “And then the library vendor adds a little bit of padding and nobody talks about what that is, but everybody adds up this stack of margin along the way. “
But of course, the semicon industry has been dealing with emerging challenges like this for its entire existence. Each new problem starts at a low stage of knowledge, beginning with Stage 0 (nobody knows the problem exists) and usually ending at about Stage 6.